An instruction set architecture (ISA) is the specification that defines how a processor executes program instructions — in effect, the chip’s working language. The choice of ISA determines which instructions a device can execute, how the processor is designed, and how the surrounding software ecosystem develops.

Arm is today the most widely used architecture in embedded devices, with a mature ecosystem and extensive development resources. Its licensing model is comparatively closed: licensees pay fees, and there are limits on how far the architecture itself can be adapted.

RISC-V is an open, royalty-free ISA. Because it is defined by a public specification, a company can design its own processor cores, peripherals and safety mechanisms around its own requirements. That lowers licensing cost, allows deeper customization, and gives more control over long-term product direction.

Automotive devices are held to demanding standards for safety, reliability and long-term supply. Vehicle programs run for a decade or more, so architecture lock-in is a real commercial risk: an open architecture keeps more of that decision in the hands of the company designing the product. This is one reason RISC-V is increasingly seen as a serious route for automotive silicon.

It is worth being clear that an open ISA does not lower the barrier to building a chip. Taking RISC-V into an automotive-grade device still requires substantial work in functional safety, reliability qualification, production process and a complete toolchain. Only teams with system-level engineering capability and production experience can carry a design from architecture through to shipping silicon.

Lysotech has taken RISC-V as its architecture and focuses on automotive-grade devices for safety-critical applications, drawing on in-house IP developed within the joint venture. We will continue to combine our engineering and industry resources to advance what RISC-V can deliver in automotive safety applications.