Responsibilities: Participate in discussions and analysis of chip specifications, functions, and performance; perform module-level and chip-level simulation verification of circuit implementations. Guide and develop test cases, execute verification plans, assist in debugging and bug localization, and prepare verification plans and reports;
Analyze project verification risks, develop mitigation strategies in advance, estimate verification workloads, and allocate verification tasks appropriately;
Undertake verification of important and complex modules.
Provide support related to chip mass-production testing and technical support for mass-produced products;
【Qualifications】
1. Master’s degree or above in microelectronics, electronic information engineering, communications, computer science, or a related field;
2. More than 5 years of UVM verification experience, with the ability to independently build a UVM verification environment;
3. Proficient in Verilog/SystemVerilog and UVM verification methodology;
4. Proficient with mainstream simulation and debugging tools such as VCS and Verdi;
5. Experience in automotive MCU chip verification is preferred;
6. Knowledge of the ISO 26262 functional safety standard is preferred.